The power semiconductor device of the kind mentioned above has been widely used as a power supply device, and has been described in the following literatures.
1. Junichi Nishizawa: "High power-lateral junction FET of the character of a triode", Nikkei Electronics, 50.about.61, Sep. 27, 1971 PA0 2. J. Nishizawa, T. Terasaki, and J. Sibata: "Field-Effect Transistor versus Analog Transistor (Static Induction Transistor)", IEEE Trans. on Electron Device, ED-22(4), 185 (1975) PA0 3. J. Nishizawa and K. Nakamura: Physiquee Appliquee, T13, 725 (1978) PA0 4. J. Nishizawa and Y. Otsubo: Tech. Dig. 1980 IEDM, 658 (1980) PA0 5. Junichi Nishizawa, Tadahiro Omi, Moken Sha, and Kaoru Hontani: "Denshi-Tsushin Institute Technical Research Report", ED81-84 (1981) PA0 6. M. Ishidoh et al: "Advanced High Frequency GTO", Proc. ISPSD, 189 (1988) PA0 7. B. J. Baliga et al: "The Evolution of Power Technology", IEEE Trans. on Electron Device, ED-31, 157 (1984) PA0 8. M. Amato et al: "Comparison of Lateral and Vertical DMOS Specific On-resistance", IEDM Tech. Dig., 736 (1985) PA0 9. B. J. Galiga: "Modern Power Device", John Wiley Sons, 350 (1987) PA0 10. H. Mitlehner et al: Proc. ISPSD, 289 (1990): "A Novel 8 kV Light-Trigger Thyristor with Over Voltage Self Protection"
The miniaturization of a semiconductor device has been effected in accordance with a progress in the high performance and low consumption of electric power, and thus the formation of a recessed portion having a high aspect ratio has been required. For instance, in order to form field-limiting rings, element separation regions and via holes in an insulated layer, and to manufacture power semiconductor devices having a notched gate structure such as a static induction (SI) thyristor, it is necessary to form a trench structure having a high aspect ratio.
The selective etching has been generally used to form the trench structure. The etching is roughly classified into isotropic etching and anisotropic etching. The isotropic etching includes wet-etching and dry-etching, and the wet-etching has an advantage, in general, that the etching speed is higher than that of the dry etching. A solution of hydrogen fluoride and nitric acid is generally used as an etching solution for the isotropic wet-etching of a silicon substrate, while a mask made of silicon oxide (SiO.sub.2), silicon nitride (Si.sub.3 N.sub.4), and silicon oxynitride (SiNO) is used.
The isotropic etching can be mainly obtained in thermally non-equilibrium of a plasma excited gas. In this case, it is known that a trench structure of a higher aspect ratio can be obtained by optimizing gas composition, gas pressure, and substrate temperature.
The above isotopic etching has a high etching speed but has s demerit that the aspect ratio could not be made high, because in case of effecting deep etching, an etching in a lateral direction is carried out underneath the mask to a substantially same extent as the etching in the depth direction.
Thus, in the past, the isotropic etching has been widely used to form the trench structure having a high aspect ratio. However it is actually impossible to form the trench structure having a depth of more than ten .mu.ms, because the isotropic etching has a low etching speed. By conducting the isotropic etching for a long time, it is theoretically possible to obtain a deep recess, but it is actually difficult to perform the etching process for a long time because the consumption of the mask is increased during a long etching so that the structure of a desired profile could not be obtained and a throughput becomes low.
The above problem will be described in more detail with reference to an example in which an SI thyristor is manufactured as one of the power semiconductor devices with the notched gate structure. FIG. 1 shows a conventional notched gate structure formed by the isotropic etching. On one surface of an N-type silicon substrate 1 there is formed a p-type anode region 2 by diffusing p-type impurities, and an anode electrode 3 is formed on the anode region. On the other surface of the silicon substrate 1 there is formed a cathode region 4 by diffusing a large amount of n-type impurities, and a cathode electrode 5 is formed on the cathode region. A recess 6 having a width W.sub.G is formed in the surface of the silicon substrate 1 and a gate region 7 is formed by diffusing p-type impurities from the bottom of the recess into the silicon substrate, and on the bottom surface of the recess a gate electrode 8 is formed to be contacted with the gate region.
The anisotropic etching has an advantage that the width W1 of the cathode region 4 is not practically narrowed because it does not practically includes the lateral etching. If the recess 6 is formed by the isotropic etching, a width W1 of the cathode region 4 becomes narrower due to the etching in the lateral direction, and therefore a ratio of a channel area to a whole surface area becomes smaller and a current capacity becomes smaller. It is generally desired that the width W1 is about 20 .mu.ms. Meanwhile a width W2 of the channel, that is, a distance between adjacent gate diffusion regions 7 is preferably about 3.about.5 .mu.ms. The above condition is satisfied by using the dry-anisotropic etching. But the long etching is required to form the deep recess 6 and it is difficult to form a recess having a depth not less than 10 .mu.ms due to the fact that the mask might be etched away during a long etching. Furthermore, during the formation of the p.sup.+ type gate region, the impurities doped in both the cathode region 4 and p.sup.+ type gate region are diffused inwardly into the silicon substrate 1, and a distance D1 between the gate region 7 and a boundary surface 9 of the n.sup.+ type cathode region and the n.sup.- type silicon substrate becomes shorter. The distance D1 is preferably not less than 5 .mu.ms, in general, but the distance becomes shorter to about 3.about.5 .mu.ms by thermal diffusion of impurities into the p.sup.+ type gate region in shallow etching depth of the recess 6. The smaller distance D1 has a disadvantage that the gate breakdown voltage might be lowered and the large current could not be cut off.
As mentioned above, the isotropic etching makes the etching time shorter, but does not make the current capacity larger because a ratio W1/W.sub.G of the width W1 of the cathode region 4 to the width W.sub.G of the recess 6 is smaller.
Now a GTO thyristor as one of the power semiconductor devices having a mesa-type structure will be described more in detailed. FIG. 2 shows a conventional mesa-type structure formed by the anisotropic etching. A p-type emitter region 102 is formed on one surface of an n.sup.- type silicon substrate 101 by diffusing p-type impurities and an anode electrode 103 is formed on the emitter region. A cathode region 104 is formed on the other surface of the silicon substrate 101 by diffusing a large amount of n-type impurities and a cathode electrode 105 is formed on the cathode region. A recess 106 having a width W.sub.G is formed in the surface of the silicon substrate 101, and a gate electrode 108 is formed on the bottom surface of the recess to be contacted with a p-type base region 107.
When the recess 106 is formed by the anisotropic etching, there is an advantage that the width W1 of the cathode region 104 does not practically become narrower because the anisotropy etching does not have the lateral etching. However, when the recess 106 is formed by the isotropic etching, the width W1 of the cathode 104 becomes narrower due to the lateral etching, and thus a ratio of the channel area to a whole surface area becomes smaller and the current capacity becomes smaller. In general, the width W1 is preferably about 5-20 .mu.ms. On the other hand, it is preferable to make a width W.sub.G of the gate as narrow as possible to such an extent that a current can be drawn from the gate in order to increase a portion through which a main current flows. These conditions could be satisfied by the anisotropic etching. However it is difficult to form the recess having a depth not less than 10 .mu.ms due to the fact a mask material might be etched for a long etching required to form the deep recess.
Like as the above mentioned SI thyristor, the isotropic etching makes etching time shorter, but a W1/W.sub.G ratio of the width W1 of the cathode 104 to the W.sub.G of the recess 106 might become smaller and a large current capacity could not be obtained.
In the isotropic etching and anisotropic etching the depressed portion 6 and the recess 106 of the conventional SI thyristor and GTO thyristor has a cross sectional configuration formed by a single curve.
Moreover, in the conventional static induction type semiconductor device, when a part of the gate region is short-circuited with the cathode region, the channel region could not be pinched-off with a reverse bias voltage because the gate current for the turn-off is bypassed through the short-circuited region. That is to say, carriers existent within the n- type region (including the channel region) at turn-off could not be swept out due to the short-circuit of the gate region to the cathode region. Therefore, in the semiconductor device of the large diameter, an influence of a gate resistance between the gate electrode and a point of a lead wire to the gate electrode could not be neglected. Consequently a large current could not be intercepted at a high speed due to a voltage drop by a gate current of the carrier flowing from the gate region to the point of the lead wire to the gate electrode at turn-off. Moreover, if an operation speed is increased by controlling lifetime of carriers, on-resistance might be increased and a conduction loss might occur.
Consequently, it is an object of this invention to solve the above mentioned problems of conventional semiconductor devices and known methods of manufacturing the same and to provide a semiconductor device with a recessed portion having a high aspect ratio and a method of manufacturing such a semiconductor device easily and precisely.
It is another object of the invention to provide a semiconductor device which can be miniaturized and can flow a larger current by increasing a ratio of a cross sectional area of a channel to a whole surface area of a semiconductor substrate.
It is still another object of the invention to provide a semiconductor device having an improved switching speed by drawing out residual carriers quickly at turn-off.